Crash 2 AMD Ryzen 7 9800X3D to Showcase 3D V-Cache 2.0

There are people who will do anything, and it seems that either they have a lot of money or AMD is supplying them with engineering samples in large quantities. And the first real images emerged from China CCD owned by Ryzen 7 9800X3Dwhere is the matrix of kernels and SRAM as 3D V-Cache 2.0. Additionally, AMD answers some interesting questions regarding vertical stacking.

We will first move on to AMD’s Q&A and then dive fully into the case and its images to briefly analyze them, since everything has been said in theory, now it remains to be seen if this is the case in practice and if We can reveal anything new, oh what was not said.

AMD answers questions about its new bottom vertical cache

The questions were only focused on finding out some details about this second generation vertical cache and as expected, its evolution is a big step forward with a copper-to-copper system. TSMC with hybrid connection.

When asked if the throughput between the SRAM and CCD matrix is ​​still 2.5 TB/s, the Reds replied that it is similar to the previous generation and increases with increasing core frequency. There really shouldn’t be any improvement here since the L3 speed is the same for both dies and we’ve already seen that. L3 throughput showed virtually no improvement from Ryzen 7000 to Ryzen 9000 clock for clock.

It is logical that the 9800X3D has a higher speed than the 7800X3D, but this is due, as AMD says, to the higher core frequency of this new CPU. And with that said, something important comes up here, because the next question was whether there were any additional benefits from placing SRAM under the CCD.

AMD responded that in addition to the thermal benefit (which we’ve discussed in detail), the additional area now allows for better power distribution.

This is completely understandable if you read the article on this topic, since now the entire SRAM area has TSVs, and their connection is made not only for L3, but also for L3. delivers energy from the substrate through specified TSVs at all its pointsOf particular importance are the sides of the CCD, which are designed differently to adapt to the specific underlying architecture.

In this regard, the last question was relevant, and the answer to it is logical: will the size of the cache memory in the SRAM die be exposed? Apparently the answer was that it was about the same size as the one the CCD came in.

Ryzen 7 9800X3D reveals what its two dies really are thanks to a splitter and CCD launch

From questions/answers we move on to what the most sensitive will find painful, but the most curious will probably enjoy. And a Chinese YouTuber took what looked like two Ryzen 7 9800X3D ES, made them “this way”, and not happy, he also unsoldered the CCD from both, including the 7800X3D, to compare the 3D V-Cache between the first generation and the second generation.

What we see below in the slide is primarily a traditional CCD with a central L3 and cores on the sides. In the next image we see SRAM bluerevealing its structure, very interesting for analysis.

Knowing what AMD used SoIC TSMC with the new system Hybrid connectionwhich we haven’t stopped talking about lately, because it’s the very near future, and it’s already here, we can say that The CtC system is interesting.

AMD’s design for the Ryzen 9000X3D with 3D V-Cache 2.0 orchestrates the relationship between the L3 caches in the CCD array and the V-Cache by strategy segmented connection and specific addressing which takes into account the difference in size and location of both caches. This system allows cache operations to remain efficient despite differences between levels.

SRAM segmentation and L3 mapping

As you can see from the video and images, each L3 section in the CCD is “mapped” to connect to its counterpart in the 3D V-Cache. Although this Ryzen 7 9800X3D’s 3D V-Cache 2.0 adds significant additional cache size to the SRAM array, It is divided into blocks that coincide with the corresponding L3 sections on the CCD.. This means that not all of the 3D V-Cache is used at the same time, but displayed and addressed
to expand the L3 parts on the main CCD.

Controlled vertical connection

Since areas and sizes are not equal, AMD uses
an interconnection system controlled at the cache controller level to redirect requests to this memory so that they use the appropriate 3D V-Cache block, depending on the L3 partition in the CCD. We will see this in the last paragraph in detail.

This allows specific addressing and reduces the latency associated with searching data in a cache volume much older. This is best seen in the image, which clearly shows the SRAM, highlighted in blue, and its internal layout.

Adaptive Bandwidth Structure

This may be another of the best kept secrets, the 3D V-Cache 2.0 inside the Ryzen 7 9800X3D. Based on what we see on the SRAM die, AMD has also adjusted the connection bandwidth between the CCD and V-Cache to balance differences in size and layout.

Featuring a Cu-to-Cu direct connection design with
scalable bandwidth channelsAMD can distribute the load so that certain parts of the L3 in the CCD have higher priority access to certain V-Cache segments. This helps avoid bottlenecks and ensures high cache performance. All through TSV, of course.

This leaves us with an intellectual structure in which Each L3 block is intelligently accessiblebut to achieve this, we will have to talk about the fourth point.

Intelligent controller and coherence protocols for L3

Finally, the cache controller in CCD is designed to
manage coherence between the original L3 cache and 3D V-Cache 2.0. These drivers are able to interpret size differences and move data sequentially, ensuring that data requests are not delayed by size differences between arrays.

For simplicity, AMD handles size and layout differences through segmented display, dedicated vertical connectivity, and advanced drivers that allow access to additional memory in the Ryzen 7 9800X3D’s 3D V-Cache 2.0 as a consistent expansion and high performance of the original L3.

This is a new system and arose due to the alteration of the L3 blocks of the CCD and its internal communicationwhich, oddly enough, Intel also seems to be using in the Core Ultra 200S, albeit in a different way, having two types of cores and Ringbus with a single 1 Step type speed, which creates problems that AMD doesn’t have, but it could be an advantage , if you decide to choose the vertical L3 as your main competitor.

As we can see, AMD’s work with this 3D V-Cache 2.0 for the Ryzen 7 9800X3D is not simply placing the die under the copper against the copper, but rather having a well thought out initial design and a very well designed SRAM, which in this case occupies the entire area CCD.